아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• 2nd Board : Under preparation first sample (w/ kernel & Memory optimization in terms of BSP)
• 3rd Board - for PROTO sample -, PCB will tape out in this week
  • Will be assembled by Jul. 20th
  • Due to external ISP in camera module, Delay of camera sample is being expected
• I2C interface for G-Sensor will connect to spearated I2C (CCI interfaces with Camera ISP / Radar sensor) 

Power Consumption

• SL did 1st test of power consumption with lower DDR Freq. (from 1.5GHz to 681MHz) as fixed clock mode, couldn't find the meaningful reduction
• Debugged via CN 6677755 to enable DDR DCVS but SL couldn't find a power reduction of power
• QC would like to ask SL to do a retest with the following applied
  • Remove all modifications for DDR fixed freq.
  • Apply all of dtsi changes (to remove UFS config)
  • Change the DDR min freq.
    • #echo 762 > /sys/class/devfreq/soc:qcom,cpu-llcc-ddr-bw/min_freq
    • #echo 762 > /sys/class/devfreq/soc:qcom,cpu0-cpu-ddr-latfloor/min_freq
    • #echo 762 > /sys/class/devfreq/soc:qcom,cpu0-llcc-ddr-lat/min_freq
    • #echo 762 > /sys/class/devfreq/soc:qcom,cpu6-cpu-ddr-latfloor/min_freq
    • #echo 762 > /sys/class/devfreq/soc:qcom,cpu6-llcc-ddr-lat/min_freq
• QC to share the reference DCN to explain DDR AOP governor

BootKPI

• SL to open new case to compare the BootKPI between the measurement of SL and QC reference

Opening Cases

아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• GN7:2.0 / Followed by vechicle 2.1 / with Radar&STR: 2.5(W/100Mbps) / 2.6(W/1Gbps Eth.)
• 2nd Board : Under implemetation of the Apps. 1st HKMC demonstration on Jun.8th
• 3rd Board - for PROTO sample -, will be assembled by Jul. 20th.
  • Due to external ISP in camera module 

Power Consumption

• SL did 1st test of power consumption with lower DDR Freq. (from 1.5GHz to 681MHz) as fixed clock mode, couldn't find the meaningful reduction
• SL to test with DCVS option for DDR(SL will open new case to query for the method)

DDR training issue of SS DRAM

• SL to reduce the length of DQS lines and QC would like to review prior to the PCB tape out of 3rd board
• SL will ask QC layout review in next week

Opening Cases

아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• 2nd Board : Under implemetation of the Apps. 1st HKMC demonstration on Jun.8th
• 3rd Board - for PROTO sample -, will be assembled by Jul. 20th.
  • Due to external ISP in camera module 

Power Consumption

• SL did 1st test of power consumption with lower DDR Freq. (from 1.5GHz to 681MHz) as fixed clock mode, couldn't find the meaningful reduction
• SL to test with DCVS option for DDR

DDR training issue of SS DRAM

• SL to reduce the length of DQS lines and QC would like to review prior to the PCB tape out of 3rd board
• SL will ask QC layout review in next week, PCB design should be finished by the middle of Jun

Opening Cases

아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• 2nd Board : Under implemetation of the Apps.
• 3rd Board - for PROTO sample -, will be assembled by Jun.
  • Due to external ISP in camera module 

Case# 06645189: weston error(SL 문현모 책임)

• QC recommend using IVI-Shell instead of desktop-shell for GST based implementation.
• Error message 'Fil to commit or flash to sdm display| err--1' is normal log due to no object to display in the screen.
• The contents on the screen will be displayed if the GST apps. starts media playback, SL to test

DDR training issue of SS DRAM

• SL to reduce the length of DQS lines and QC would like to review prior to the PCB tape out of 3rd board
• SL will ask QC schematic review in next week, PCB design should be finished by the middle of Jun

Opening Cases

실질적으로 프로젝트를 시작한지 약 3개월이 지났습니다만 처음으로 주간 회의를 진행하게 되었습니다.  필요한 부분 있으시면 금일 회의시간에도 말씀 드렸습니다만 매주 목요일까지 논의가 필요한 agenda나 escalated case등을 공유해 주시면 담당자 분들과 같이 참석할 수 있도록 내부 조율토록 하겠습니다.
아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• 2nd Board - for PROTO sample - will be assembled by Apr. 17th, will be finished the bring up by the end of Apr.
  • SA6155P.LV.2.0 CS3 is entitled, SL will finish the migration prior to the 2nd board assemble
• Around 25 partitions in QC reference will be removed based on QC guidance
• Under checking the BootKPI on the target system, SL will open new case if there is a question
• Under 2GB in the eMMC is allowed if the Ethernet-AVB is disabled, SL wants to optimize the boot storage below 2GB - only A/B partition -

Case# 06574938: Hot to fix DDR frequency - LPDDR clock 고정 CASE 이슈
SL's question: 주차 모드에서 소모전류를 줄이기 위해서 LPDDR clock 고정 방법을 Case로 문의했었는데, 아래와 같이 768MHz에 이슈가 있다고 합니다. 자세한 내용에 대해서 설명이 가능한지 확인 좀 부탁드립니다.
QC update in the case: There is some issue in some vendors' DDR in 768Mhz during booting. So we remove the 768MHz in SA6155 SKUs as the operating clock. The DDR training is also skipped for 768Mhz.
QC would like to recommend using 681Mhz because the 768MHz isn't PoRed in SA6155P.LV.2.0 SP, Available running frequencies are described in document of '80-PK753-26 SA6155_Clock_Plan'

BootKPI

• SL's question: 고객사(현대자동차)에서 2.5세대는 부팅속도를 2.5초로 사양 설정을 할려고 하는데, 사양 만족이 가능한지 문의를 하고 있습니다.  STR mode 적용했을 경우에 해당 사양을 만족하는 것으로 알고 있습니다. 저희가 이번 NRE 항목 논의 시 STR mode에 대해서는 요청을 하지 않았던 것으로 알고 있습니다. 현재 저희 소스에서 해당 기능이 지원이 가능한지 알고 싶습니다. 지원하지 않으면 해당 기능을 지원하기 위한 방안이 있는지도 검토 부탁드립니다.
• The STR is being supported in the LV.2.0 SP, and about 2.1sec is the KPI to start 'the Video Playback & Recoding' in the cold booting.  SL needs to optimize the application to meet the BootKPI from OEM.
• FYI, The BLTN-CAM 2.5 means a next level production that requires RADAR sensor

Dummy frame encoding in CSI failure stage

• SL's question: CS3 버전 릴리즈 노트 내용 중에 6.2.9 video 항목에 아래와 같은 문구가 표시되어 있습니다.  해당 문구가 CSI로 영상이 입력되지 않을 경우에 Dummy frame를 encoding한다는 내용이 맞나요? 문구 내용이 짧아서 저희가 이해한 내용이 맞는지 확인 좀 부탁드립니다.

• The feature is being supported for HKMC user scenario

Chipcode accessing via git client

• QC thinking the specific configuration per customer internet connection is required in the gitconfig
• QC will support it once SL create a new case

Case# 06564989: SA6155P.LV.2.0 CS3 build issue

• CAF is terminated as the of Mar., Some recipes that refer to CAF in Yocto are being issued.
• QC to provide patches

DDR training issue of SS DRAM

• DDR training is still failed on 681Mhz in SS PVL Memory, no technical review by QC is possible due to limitation of the clue / facility
• SL would like to check the DDR status of PVL SS DRAM in terms of HW, including QDUTT test, on top of QC reference - ADP -
• New DDR Test plan (QC did onsite support at Mar. 30th)
  • QC shared DDR test without QC validation is difficult to support, requires self-validation by the SL
  • Action items - SL will follow it up in 2nd target system (After Apr. 18th)
    • SL to run QMVS test (DDR stress Test – QMESA, reboot etc.) at low/room/high temperature
    • SL to do QDUTT Shmoo test for each DDR Frequencies
    • SL to do DDR Re-training test every boot for multiple devices
    • SL to collaborate DRAM PI / SI Analysis with DDR vendor(SS)
    • QC shared the guidance the reference document for QMVS/QDUTT testing
      • QC to check the separate license is required or not for the QMVS

Opening Cases

금주 주간 회의 내용을 아래와 같이 공유해 드리오니 업무에 참고하여 주십시오.  (Action items: SL / QC)

Customer schedule

Status

• 2nd Board - for PROTO sample - will be assembled by Apr. 18th, will be finished the bring up by the end of Apr.
  • SA6155P.LV.2.0 CS3 is entitled, SL will finish the migration prior to the 2nd board assemble
• Around 25 partitions in QC reference will be removed based on QC guidance

Chipcode accessing via git client

• QC thinking the specific configuration per customer internet connection is required in the gitconfig
• QC will support it once SL create a new case
  

Case# 06564989: SA6155P.LV.2.0 CS3 build issue

• CAF is terminated as the of Mar., Some recipes that refer to CAF in Yocto are being issued.
• QC will provide patches by the end of next week

DDR training issue of SS DRAM

• DDR training is still failed on 681Mhz in SS PVL Memory, no technical review by QC is possible due to limitation of the clue / facility
• SL would like to check the DDR status of PVL SS DRAM in terms of HW, including QDUTT test, on top of QC reference - ADP -
• New DDR Test plan (QC did onsite support at Mar. 30th)
  • QC shared DDR test without QC validation is difficult to support, requires self-validation by the SL
  • Action items - SL will follow it up in 2nd target system (After Apr. 18th)
    • SL to run QMVS test (DDR stress Test – QMESA, reboot etc.) at low/room/high temperature
    • SL to do QDUTT Shmoo test for each DDR Frequencies
    • SL to do DDR Re-training test every boot for multiple devices
    • SL to collaborate DRAM PI / SI Analysis with DDR vendor(SS)
    • QC to guide the reference document for QMVS/QDUTT testing
      

Display scenario [CLOSED]

• Scenario A: Display output thru DSI
• 
• Display setting on weston needs to set as 2560x720
• SL can display the camera output via GST (with window size & position) without GPU composition in advance

• SL had used GST compositor (SW CSC) and observed around 10% CPU utilization, checked the CPU utilization has reduced by qvconv instead GST compositor
  • SL verified the dual display output via single display without a GST compositor

Opening cases

금주 주간 회의 내용을 아래와 같이 공유해 드리오니 업무에 참고하여 주십시오.  (Action items: SL / QC)

Customer schedule

Status

• 2nd Board - for PROTO sample - will be assembled by Apr. 15th, will be finished the bring up by the end of Apr.
  • SA6155P.LV.2.0 CS3 is entitled, SL will finish the migration prior to the 2nd board assemble

DDR training issue of SS DRAM

• DDR training is still failed on 681Mhz in SS PVL Memory, no technical review by QC is possible due to limitation of the clue / facility
• SL would like to check the DDR status of PVL SS DRAM in terms of HW, including QDUTT test, on top of QC reference - ADP -
• New DDR Test plan (QC did onsite support at Mar. 30th)
  • QC shared DDR test without QC validation is difficult to support, requires self-validation by the SL
  • Action items
    • SL to run QMVS test (DDR stress Test – QMESA, reboot etc.) at low/room/high temperature
    • SL to do QDUTT Shmoo test for each DDR Frequencies
    • SL to do DDR Re-training test every boot for multiple devices
    • SL to collaborate DRAM PI / SI Analysis with DDR vendor(SS)
    • QC to guide the reference document for QMVS/QDUTT testing
      

Display scenario

• Scenario A: Display output thru DSI
• 
• Display setting on weston needs to set as 2560x720
• SL can display the camera output via GST (with window size & position) without GPU composition in advance

• SL had used GST compositor (SW CSC) and observed around 10% CPU utilization, checked the CPU utilization has reduced by qvconv instead GST compositor
  • SL to share the GST command via new case for QC review/recommendation
    

Opening cases

금주 주간 회의 내용을 아래와 같이 공유해 드리오니 업무에 참고하여 주십시오.  (Action items: SL / QC)

아울러 금일 회의 후 고민해 본 결과 Dual camera output via 2560x720 관련하여 조금 더 자세하게 논의하는 것이 좋은 것 같다는 생각이 들었습니다.
사용하시려는 Display port – DP or DSI – 에 대한 정확한 사양과 함께 전체적인 user scenario를 차주 목요일 전까지 저희에게 공유 요청 드립니다.
다음 주간 회의에는 저희 Display / Graphic 담당자 분들과 함께 해당 내용에 대해 주요 논의하는 것을 주요 의제로 하려고 하오니 참고하시어 지원 요청 드립니다.

Customer schedule

Status

• 2nd Board - for PROTO sample - will be assembled by Apr. 15th, will be finished the bring up by the end of Apr.
  • SA6155P.LV.2.0 CS3 is required, under communication in QC to open the LV.2.0 SP in the ChipCode

DDR training issue of SS DRAM

• DDR training is still failed on 681Mhz in SS PVL Memory, no technical review by QC is possible due to limitation of the clue / facility
• SL would like to check the DDR status of PVL SS DRAM in terms of HW, including QDUTT test, on top of QC reference - ADP -
• Action items
  • QC to support the measurement by the QC reference boards - SL: non PVL SS DRAM / QC: PVL SS DRAM -
  • SL to check the schedule of SI measurement (by Mar. 27th)

SW update solution

• 'A/B switch' is implemented in LV.2.0 SP to support the boot partition switching
• SL to open new case to get the explanation/manual about the 'A/B switch' 

Case# 06549786: SW update solution

• 'A/B switch' is implemented in LV.2.0 SP to support the boot partition switching
• There is a bug of abctl in CS2, QC recommends using abctl on CS3

gStreamer

• QC supports the following GST pipelines for HKMC built-in CAM project
  • qCarCamSrc: GST pipeline to connect AIS server with gStreamer
  • VideoBlend: HW - GPU - assisted GST pipeline for image blending
  • qvconv: HW - GPU - assisted GST pipeline for video format conversion
• SL can ask for additional explanation via case for the QC GST pipelines

WiFi [DONE]

• Finish the NXP WiFi bring-up, verified the operation

Opening cases

실질적으로 프로젝트를 시작한지 약 3개월이 지났습니다만 처음으로 주간 회의를 진행하게 되었습니다.  필요한 부분 있으시면 금일 회의시간에도 말씀 드렸습니다만 매주 목요일까지 논의가 필요한 agenda나 escalated case등을 공유해 주시면 담당자 분들과 같이 참석할 수 있도록 내부 조율토록 하겠습니다.
아래 내용은 금주에 논의된 내용이오니 업무에 참고하여 주십시오. (Action Items : by SL / by QC)

Customer schedule

Status

• 2nd Board - for PROTO sample - will be assembled by Apr. 15th, will be finished the bring up by the end of Apr.
  • SA6155P.LV.2.0 CS3 is required, SL to send an email for its accessing request to QC sales team
• SL verified basic functions of Video/Audio encoding 
• Under tunning of Audio encoding quality, QC ECNR for single Mic. is under consideration if the HW improvement isn't enough

DDR training issue of SS DRAM

• Will discuss in next weekly conference

SW update solution

• 'A/B switch' is implemented in LV.2.0 SP to support the boot partition switching
• SL to open new case to get the explanation/manual about the 'A/B switch' 

Security

• SL can refer to the document of '80-PK753-40: SA6155 TrustZone and Security Overview' for the detail
• QC support the following security features in LV.2.0 SP
  • Secure boot (Bootloader) / AVB-2.0 (Kernel & System): System integrity
  • Secure Storage (FDE): Partition based file encryption/description (FDE)
  • TrustZone: to support TA / KeyMaster / QSEE

gStreamer

• QC supports the following GST pipelines for HKMC built-in CAM project
  • qCarCamSrc: GST pipeline to connect AIS server with gStreamer
  • VideoBlend: HW - GPU - assisted GST pipeline for image blending
  • qvconv: HW - GPU - assisted GST pipeline for video format conversion
• SL is under trouble by 0 byte issue in some GST use cases, SL to open new case for QC support

WiFi

• Case 06538669: Kernel/Security option for WiFi .ko file loading 
• SL could build the NXP WiFi driver successfully by QC support via separate case
• In trouble loading the .ko file, wants QC support in terms of Linux Kernel/Security

Opening cases